1. Field of the Invention
The present invention relates to the field of manufacturing of semiconductor devices, and, more particularly, to the measurement of stress in semiconductor structures.
2. Description of the Related Art
Integrated circuits comprise a large number of individual circuit elements such as, e.g., transistors, capacitors and resistors. These elements are connected internally via electrically conductive lines to form complex circuits such as memory devices, logic devices, and microprocessors. An improvement in the performance of integrated circuits requires a reduction of feature sizes. In addition to an increase in the speed of operation due to reduced signal propagation times, reduced feature sizes allow an increase in the number of functional elements in the circuit in order to extend its functionality. Today, advanced semiconductor structures can comprise features having a size of 0.1 μm or less.
As the size of structural elements such as circuit elements and electrically conductive lines decreases, the effects of stress become more and more important. Electrically conductive lines are typically embedded in an interlayer dielectric. If stress occurs in the interlayer dielectric, the mechanical connection between the electrically conductive lines and the interlayer dielectric and/or structural elements they are connected to, such as other electrically conductive lines and circuit elements, can be weakened. This may adversely affect the stability of the integrated circuit and lead to an increased contact resistance between the electrically conductive lines. The increased contact resistance, in turn, may adversely affect the functioning of the integrated circuit, and may lead to a quick deterioration of the circuit due to an excessive formation of heat. Stress may also lead to a detachment of the electrically conductive line from a structural element it is connected to, which can result in a failure of the integrated circuit.
Stress in the interlayer dielectric may be particularly disadvantageous if the interlayer dielectric comprises low-k materials that are employed to decrease signal propagation delays due to parasitic capacitances. Since these materials have comparatively weak bondings, the stress may even lead to the formation of cracks and/or to the detaching of electrically conductive lines from the interlayer dielectric.
Conversely, stress may be intentionally utilized to enhance the performance of circuit elements. Tensile or compressive stress in a semiconductor material may result in a modified mobility of electrons and holes. Creating tensile stress increases the mobility of electrons, wherein, depending on the magnitude of the tensile stress, an increase by up to 20% may be achieved, which, in turn, directly translates into a corresponding increase in the conductivity. The stress-induced increase in the mobility of electrons may be used to enhance the performance of N-type field effect transistors by increasing the mobility of charge carriers in the channel region. On the other hand, compressive stress in the channel region of a P-type field effect transistor increases the mobility of holes, which may be used to enhance the performance of the transistor.
In order to create tensile or compressive stress in the channel region of a transistor, it has been proposed to introduce, for example, a silicon/germanium layer or a silicon/carbon layer into or below the channel region. Alternatively, stress in the channel region may be created by depositing a strained spacer layer and etching the strained spacer layer to create spacer elements having tensile or compressive stress adjacent the gate electrode.
Thus, stress in an integrated circuit may significantly affect the performance of the circuit. Hence, a measurement of stress in a semiconductor structure may be important in the design of an integrated circuit or a structural element thereof.
A method for measuring a stress in a semiconductor structure according to the state of the art will now be described. Typically, the curvature of a substrate is measured using a profiler (profilometer), which is an instrument adapted to scan a surface of the substrate by means of a stylus. Subsequently, a layer of a material is deposited on the substrate. If the deposition of the layer of material generates stress, the substrate is bent. Hence, the curvature of the substrate is altered. After the deposition of the layer, the curvature of the substrate is measured once again. Then, the stress in the film is calculated from the curvatures measured before and after the deposition of the layer by means of an equation derived by means of the theory of elasticity.
One problem with the conventional measurement of stress in a semiconductor structure is that the thickness of the substrate enters into the calculation of the stress. The thicker the substrate, the smaller the alteration of the curvature resulting from a particular stress and, thus, the less sensitive the measurement. Thin substrates, on the other hand, are easily deformed by gravity, which may also adversely affect the precision of the measurement.
Another problem of the conventional measurement of stress in a semiconductor structure is that the curvature of the substrate must be measured over a range of up to several centimeters, such that inhomogeneities of the substrate and/or the deposited layer may lead to erroneous results in the measurement.
Yet another problem of the conventional measurement of stress in a semiconductor structure is that to measure stress between a first material and a second material, a substrate consisting of one of the materials is provided. This may significantly increase the costs of the measurement process, in particular if materials that are expensive and/or difficult to handle are investigated.
Yet another problem of the conventional measurement of stress in a semiconductor structure is that the measurement cannot be performed in situ while the semiconductor structure is being processed.
In view of the above-mentioned problems, a need exists for a system and method allowing precise measurement of stress in a semiconductor structure.